Mht Cet
Semiconductor Devices And Logic Gates
MHT CET 2025 26th April Evening Shift
MCQ+1 / -02025
In a certain 2 -inputs logic gate, when inputs $\mathrm{A}=0$ and $\mathrm{B}=0$, then output $\mathrm{C}=1$. And also when inputs $\mathrm{A}=0, \mathrm{~B}=1$, then again output $\mathrm{C}=1$. The gate must be
