Mht Cet
Semiconductor Devices And Logic Gates
MHT CET 2024 9th May Morning Shift
MCQ+1 / -02024
In the logic circuit diagram, when all the four inputs $\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D}$ are one, the outputs $\mathrm{Y}_1, \mathrm{Y}_2, \mathrm{Y}_3$ are respectively $(1,1,0)$. When all the inputs $\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D}$ are changed to 'zero', the outputs $\mathrm{Y}_1, \mathrm{Y}_2, \mathrm{Y}_3$ respectively change to

